Temporal Veri cation Diagrams ?
نویسندگان
چکیده
Most formal approaches to the veriication of temporal properties of reactive programs infer temporal conclusions from veriication conditions that are state formulas, i.e., contain no temporal operators. These proofs can often be eeectively presented by the use of veriica-tion diagrams. In this paper, we present a self-contained presentation of veriication diagrams for proving various temporal properties. Beginning with safety properties, we present WAIT-FOR and INVARIANCE diagrams for proving wait-for (precedence) and invariance formulas. Proceeding to liveness properties, we present veriication diagrams for response properties that require a bounded number of helpful steps (CHAIN diagrams) and response properties that require an unbounded number of helpful steps (RANK diagrams). Additional types of diagrams are proposed for handling response properties for parameterized programs (e.g., PRANK diagrams) and response properties that rely on the full spectrum of fairness requirements, including compassionate helpful transitions (e.g., F-CHAIN diagrams).
منابع مشابه
Decomposing, Transforming and Composing Diagrams: The Joys of Modular Veri cation
The paper proposes a modular framework for the veri cation of temporal logic properties of systems based on the deductive transformation and composition of diagrams. The diagrams represent abstractions of the modules composing the system, together with information about the environment of the modules. The proof of a temporal speci cation is constructed with the help of diagram transformation an...
متن کاملStep: the Stanford Temporal Prover S Step: the Stanford Temporal Prover
We describe the Stanford Temporal Prover (STeP), a system being developed to support the computer-aided formal veri cation of concurrent and reactive systems based on temporal speci cations. Unlike systems based on model-checking, STeP is not restricted to nite-state systems. It combines model checking and deductive methods to allow the veri cation of a broad class of systems, including program...
متن کاملA Logical Formalization of Hardware Design Diagrams
Diagrams have been left as an informal tool in hardware reasoning, thus rendering them unacceptable representations within formal reasoning systems. We demonstrate some advantages of formally supporting diagrams in hardware veri cation systems via a simple example and provide a logical formalization of hardware diagrams upon which we are constructing a veri cation tool.
متن کاملDeductive Veri cation of Real - time SystemsUsing STeP ?
We present a modular framework for proving temporal properties of real-time systems, based on clocked transition systems and linear-time temporal logic. We show how deductive veriication rules, veriication diagrams, and automatic invariant generation can be used to establish properties of real-time systems in this framework. As an example , we present the mechanical veriication of the generaliz...
متن کاملVeri cation of the MDG Components Library in HOL
The MDG system is a decision diagram based veri cation tool, primarily designed for hardware veri cation. It is based on Multiway decision diagrams|an extension of the traditional ROBDD approach. In this paper we describe the formal veri cation of the component library of the MDG system, using HOL. The hardware component library, whilst relatively simple, has been a source of errors in an earli...
متن کاملFormal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
node with a fresh abstract variable. However, the reachable state spaceis unnecessarily enlarged since states that are not within processor-like loops arealso generalized. As a trade-o , we propose a heuristic solution to this problem:After a certain number of state transitions (speci ed by the user), if the MDGsize of the frontier-set keeps increasing, the value of each state v...
متن کامل